1. Field of the Invention
The present invention relates to integrated circuit design and fabrication. More specifically, the present invention relates to a method and an apparatus to determine mask layouts for a multiple patterning process.
2. Related Art
Dramatic improvements in semiconductor integration densities have largely been achieved through corresponding improvements in semiconductor manufacturing technologies. As semiconductor manufacturing technologies move into the deep sub-micron era, the semiconductor industry is considering a number of new technologies, such as, extreme ultraviolet (EUV) lithography and immersion lithography. Unfortunately, these technologies may not be ready for production in the near future.
Multiple patterning is a promising technology that can increase integration densities using today's process technologies. This technology uses multiple masks to realize features on a wafer. It is desirable to develop systems and techniques that can determine mask layouts for a multiple patterning process.